ASIC Physical Design Engineer - Synthesis and Timing - (Associate or Experienced)

Minimum Qualifications

This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required. Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 1+ years of practical experience in synthesis and static timing analysis (STA) Solid understanding of timing convergence, constraints generation/management, and logic synthesis at block or full‑chip level Familiarity with DFT, UPF/CPF power intent, ECO implementation, and signoff flows Experience with industry-standard EDA tools for synthesis, STA, and equivalence checking Proficiency in scripting (Tcl, Python, Perl) for flow automation and analysis Strong analytical, problem‑solving, and communication skills